1. Field of the Invention
The present invention relates to integrated circuits (preferably, integrated nonvolatile memory circuits) that are operable either in a first mode in which input/output (I/O) pads are connected through buffer circuitry to internal circuitry such as an internal logic circuit or an array of memory cells (so that data can be written to the cells through an input buffer, or data can be read from the cells through an output buffer), or in a test mode in which the I/O pads are connected directly to the internal circuitry (such as an internal logic circuit or a memory cell array).
2. Description of Related Art
Nonvolatile memory chips (integrated circuits) with higher density are being introduced to the market each day. In order to achieve higher density, chip manufacturers must continually decrease the size of elements of the chips (such as the size of each cell of a memory array implemented in each chip). With memory array cells having submicron feature sizes, the slightest change in processing of one memory cell relative to another during manufacture results in a big difference in the behavior of the cells with respect to each other.
Many conventional memory chips operate in either a test mode in which input/output ("I/O") pads are connected directly to an array of memory cells, or in a "normal" (or "active") mode in which the I/O pads are connected through buffer circuitry to the array of memory cells. In the latter mode (the "normal" mode) the chip can perform read/write operations in which data is written to selected ones of the cells through an input buffer (or data is read from selected ones of the cells through an output buffer).
FIG. 1 is a simplified block diagram of a conventional memory chip of this type. Integrated circuit 3 of FIG. 1 includes at least one I/O pad 30 (for asserting output data to an external device or receiving input data from an external device), input/output buffer circuit 10 for I/O pad 30, test mode switch M1, address buffers A0 through Ap for receiving memory address bits from an external device, row decoder circuit (X address decoder) 12, column multiplexer circuit (Y multiplexer) 14, and memory array 16 (comprising columns of memory cells, which can be nonvolatile memory cells, such as column 16A). Each of address buffers A0 through Ap includes an address bit pad for receiving (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym.
I/O buffer circuit 10 includes a "write" branch and a "read" branch." The write branch comprises input buffer 18. The read branch comprises sense amplifier 19 and output buffer 20. In the normal operating mode of chip 3 of FIG. 1, chip 3 executes a write operation by receiving data (to be written to memory array 16) from an external device at I/O pad 30, buffering the data in the write branch, and then writing the data to the appropriate memory cell. Also in this normal operating mode, chip 3 can be controlled to execute a read operation in which it amplifies and buffers data (that has been read from array 16) in the read branch, and then asserts this data to I/O pad 30.
Although only one I/O pad (pad 30) is shown in FIG. 1, typical implementations of the FIG. 1 circuit include a plurality of I/O pads, and each I/O pad is buffered by an I/O buffer circuit similar or identical to circuit 10. For example, one implementation of the FIG. 1 circuit includes eight I/O pads, eight buffer circuits identical to circuit 10, one line connected between the output of the output buffer 20 of each buffer circuit and one of the I/O pads (so that eight data bits can be read in parallel from buffers 20 to the pads), and one line connected between the input of the input buffer 18 of each buffer circuit and one of the I/O pads (so that eight data bits can be written in parallel from the pads to buffers 18). Each I/O pad (including I/O pad 30) typically has high impedance when the output buffer is not enabled.
Each of the cells (storage locations) of memory array circuit 16 is indexed by a row index (an "X" index determined by decoder circuit 12) and a column index (a "Y" index output determined by circuit 14). FIG. 2 is a simplified schematic diagram of two columns of cells of memory array 16 (with one column, e.g., the column on the right, corresponding to column 16A of FIG. 1). The column on the left side of FIG. 2 comprises "n" memory cells, each cell implemented by one of floating-gate N-channel transistors N1, N3, . . . , Nn. The drain of each of transistors N1-Nn is connected to bitline 13, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The column on the right side of FIG. 2 also comprises "In" memory cells, each cell implemented by one of floating-gate N-channel transistors N2, N4, . . . , Nm. The drain of each of transistors N2-Nm is connected to bitline 15, and the gate of each is connected to a different wordline (a different one of wordline 0 through wordline n). The source of each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm is held at a source potential (which is usually ground potential for the chip during a read or programming operation).
Each memory cell is a nonvolatile memory cell since each of transistors N1, N3, . . . , Nn, and N2, N4, . . . , Nm has a floating gate capable of semipermanent charge storage. The current drawn by each cell (i.e., by each of transistors N1, N3, Nn, and N2, N4, . . . , Nm) depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored "semipermanently" in the corresponding cell. In cases in which each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm is a flash memory device (as indicated in FIG. 2 by the symbol employed to denote each of transistors N1, N3, . . . , Nn, N2, N4, . . . , and Nm), the charge stored on the floating gate of each is erasable (and thus the data value stored by each cell is erasable) by appropriately changing the voltage applied to the gate and source (in a well known manner).
In response to address bits Y0-Ym, circuit 14 (of FIG. 1) determines a column address which selects one of the columns of memory cells of array 16 (connecting the bitline of the selected column to Node 1 of FIG. 1), and in response to address bits X0-Xn, circuit 12 (of FIG. 1) determines a row address which selects one cell in the selected column. Consider an example in which the column address selects the column on the right side of FIG. 2 (the column including bitline 15) and the row address selects the cell connected along wordline 0 (the cell comprising transistor N2). To read the data value stored in the selected cell, a signal (a current signal) indicative of such value is provided from the cell's drain (the drain of transistor N2, in the example), through bitline 15 and circuit 14, to node 1 of FIG. 1. To write a data value to the selected cell, a signal indicative of such value is provided to the cell's gate and drain (the gate and drain of transistor N2, in the example).
In the test mode of the FIG. 1 chip, a selected cell of array 16 is connected directly to I/O pad 30 (or directly to several I/O pads including pad 30 and other I/O pads) so that a current/voltage characterization can be performed on the selected cell as follows. The voltage at the cell's drain (the potential at which bitline 15 is held, in the example) is controllable since the selected bitline is directly connected to an external device through I/O pad 30 (thus, the external device can vary the voltage at which bitline 15 is held, in the example). By sweeping the voltage on I/O pad 30 during the test mode and monitoring the resulting current (the current flowing from the selected cell's drain through bitline 15, circuit 14, Node 1, and switch M1 to I/O pad 30), a current/voltage curve for the cell is obtained.
It should be appreciated that in variations on the FIG. 1 circuit (and in alternative embodiments of the invention to be described below), during the test mode, the voltage at the gate of the selected cell (in addition to or instead of the voltage at the cell's drain) is controlled (e.g., via direct connection of the gate through access to the wordline driver supply through a pad). In the test mode of each such variation (and of each embodiment of the invention), the voltage on the selected I/O pad is swept (to vary the voltage at the selected cell's drain), and the current at the selected I/O pad is monitored to obtain a current/voltage curve for the cell. Then, voltage of the gate of the selected cell is changed and by sweeping the voltage on the I/O pad and monitoring the current at the selected I/O pad another current/voltage curve for the cell is obtained. When this process is repeated for each of a sequence of gate voltages, a family of current/voltage curves for the cell is determined.
With reference again to FIG. 1, the function of switch M1 is to switch the FIG. 1 chip between its a test mode and its normal operating mode. Conventionally, switch M1 is an NMOS transistor whose gate receives a control signal ("Test Mode Enable") from internal control logic of the chip. The source and drain of M1 are connected in series with I/O pad 30 and circuit 14. Switch M1 operates as follows in response to the control signal:
M1 is "on" when Test Mode Enable is high (when the value of Test Mode Enable triggers the "test" mode of FIG. 1), and thus M1 functions as a pass transistor which passes a signal (a "test" signal) indicative of test data to be written to or read from a selected cell of array 16 (e.g., a current signal indicative of test data read from the selected cell) between its source and drain (and thus between I/O pad 30 and the selected cell of array 16) without passing such data signal through buffer 10; and
M1 is "off" when Test Mode Enable is low (when the value of Test Mode Enable triggers the "normal" operating mode of FIG. 1), so that signals (indicative of data to be written to memory array 16) provided from an external device to I/O pad 30 are buffered in input buffer 18 and then asserted to memory array 16, or signals (indicative of data read from memory array 16) are asserted from memory array 16 to sense amplifier 19, amplified in amplifier circuit 19, and then buffered in output buffer 20 and asserted to I/O pad 30. Typically, the "low" value of Test Mode Enable is ground potential.
In the normal operating mode of FIG. 1 (with M1 "off"), the FIG. 1 circuit executes a write operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 determines a column address (which selects one of the columns of memory cells of array 16, such as column 16A), and circuit 12 determines a row address (which selects one cell in the selected column). In response to a write command (supplied from control circuitry not shown in FIG. 1), a signal (indicative of data) present at the output of input buffer 18 (which has been enabled by the appropriate level of the control signal "DATA DRIVER ON") is asserted through circuit 14 to the cell of array 16 determined by the row and column address (e.g., to the drain of such cell). During such write operation, output buffer 20 is disabled (in response to an appropriate level of control signal OUTPUT ENABLE).
A data latch (not shown) is typically provided between input buffer 18 and I/O pad 30 for storing data (to be written to a memory cell) received from I/O pad 30. When the latched data is sent to input buffer 18, input buffer 18 produces a voltage at Node 1 which is applied to the selected memory cell. Input buffer 18 is typically implemented as a tri-statable driver having an output which can be placed in a high impedance mode (and thus disabled) during a read operation. Input buffer 18 is disabled by asserting (to input buffer 18) an appropriate level of the control signal DATA DRIVER ON. In some implementations, the functions of the latch and input buffer 18 are combined into a single device.
In the normal operating mode (with M1 "off"), the FIG. 1 circuit executes a read operation as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to address decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to circuit 14. In response to these address bits, circuit 14 asserts a column address to memory array 16 (which selects one of the columns of memory cells, such as column 16A), and circuit 12 asserts a row address to memory array 16 (which selects one cell in the selected column). In response to a read command (supplied from control circuitry not shown in FIG. 1), a current signal indicative of a data value stored in the cell of array 16 (a "data signal") determined by the row and column address is supplied from the drain of the selected cell through the bitline of the selected cell and then through circuit 14 to sense amplifier 19. This data signal is amplified in amplifier 19, buffered in output buffer 20 (which is enabled by an appropriate level of control signal "OUTPUT ENABLE"), and finally asserted at I/O pad 30. During such read operation, input buffer 18 is disabled (in response to an appropriate level of control signal DATA DRIVER ON).
When reading a selected cell of array 16, if the cell is in an erased state, the cell will conduct a first current which is converted to a first voltage in sense amplifier 19. If the cell is in a programmed state, it will conduct a second current which is converted to a second voltage in sense amplifier 19. Sense amplifier 19 determines the state of the cell (i.e., whether it is programmed or erased corresponding to a binary value of 0 or 1, respectively) by comparing the voltage indicative of the cell state to a reference voltage. The outcome of this comparison is an output which is either high or low (corresponding to a digital value of one or zero) which sense amplifier 19 sends to output buffer 20, which in turn asserts a corresponding data signal to I/O pad 30 (from which it can be accessed by an external device).
During the test mode, input buffer 18, sense amplifier 19, and output buffer 20 are all disabled (in response to appropriate levels of their respective control signals DATA DRIVER ON, SENSE AMPLIFIER ENABLE, and OUTPUT ENABLE).
During a write operation in the normal operating mode, control signal SENSE AMPLIFIER ENABLE disables sense amplifier 19. During a read operation in the normal operating mode, circuit 14 is employed to access the desired cell in array 16 and control signal SENSE AMPLIFIER ENABLE enables sense amplifier 19 so that sense amplifier 19 can determine the state of the selected cell as described.
It is important during a write operation (in the normal operating mode) to provide the wordline of the selected cell with the proper voltage and the drain of the selected cell with the appropriate voltage level (the voltage determined by the output of input buffer 18), in order to successfully write data to the cell without damaging the cell.
However, two serious problems often arise during the normal operating mode of conventional memory chip 3 of FIG. 1. These problems will next be described with reference to FIG. 3. When conventional I/O buffer 10 executes a "write" operation (during the normal operating mode), it is desired that conventional switch M1 (an NMOS transistor) is "off" and thus the gate of switch M1 is grounded as shown in FIG. 3 (ground voltage is the "low" level of Test Mode Enable applied to M1's gate). However, even with the gate of switch M1 grounded, switch M1 may undesirably turn "on" if the voltage at I/O pad 30 falls sufficiently low (e.g., to -1 volt, where M1 has a threshold voltage V.sub.th equal to about 0.5 volt) during the normal operating mode (e.g., during a write operation in the normal operating mode). If switch M1 undesirably turns "on" at this time, the voltage (at Node 1) applied to the selected memory cell is undesirably affected by the voltage at I/O pad 30. For example, with switch M1 undesirably "on" during a write operation in the normal operation mode, even if the output of buffer 18 (which is suppose to have a high value, such as five or six volts, in response to a low voltage at I/O pad 30, such as -1 volt), switch M1 (configured as a pass transistor) will undesirably pull Node 1 down and load down the driver of buffer 18. This will change the level of the voltage on the drain of the selected memory cell. This effect can cause a failure of the programming of the selected memory cell.
A second problem can arise when the circuit of FIG. 1 (and FIG. 3) executes a read operation in the normal operation mode. When a programmed bit is read from a selected memory cell, the selected column of cells (and thus Node 1) will go to a voltage higher than sense amplifier 19's trip point, with the result that the output voltage at I/O pad 30 (the data value read from the selected cell) goes from high to low. If however, switch M1 undesirably turns "on" due to inductive coupling of I/O pad 30 to a negative value (or the like) during such read operation, M1 will pull Node 1 down to a voltage lower than sense amplifier 19's trip point, with the result that the output voltage at I/O pad 30 goes from low to high. This effect causes a voltage oscillation at I/O pad 30, which can cause an incorrect data value to be read from the selected memory cell.
The present invention provides a test mode switch that is not subject to the problems described in the two previous paragraphs.